FIG. 1 is a block diagram of a traditional prior art N-to-1 multiplexer ("MUX") 100 that comprises N data inputs 105, N select inputs 110, and a data output 115. At any given time, MUX 100 provides a single data path between one of the N data inputs 105 and data output 115 in response to asserting one of the N select inputs. Decoding logic 125 is typically provided to decode a select signal 130 and to assert the correct one of the N select inputs 110 in response the decoding of the select signal 130. Select signal 130 typically comprises a total of log.sub.2 N conductors and is provided to simplify the interface between MUX 100 and the circuitry that determines which of the N data inputs 105 is to be coupled to data output 115.
FIG. 2 shows a static N-to-1 multiplexer architecture according to the prior art. To simplify discussion, N is equal to two (2). Multiplexer 200 is shown as generally comprising N input buffers 210-211, N pass gates 220-221 controlled by N select inputs S0 and S1, and a single output buffer 235. Input buffers 210 and 211 are shown as inverters and are connected to receive data signals from data inputs D0 and D1, respectively. The output of input buffer 210 is coupled to a first terminal of pass gate 220, and the output of input buffer 211 is coupled to a first terminal of pass gate 221. The second terminals of pass gates 220 and 221 are both coupled to common node 230. Pass gates 220 and 221 act as switches for coupling the outputs of input buffers 210 and 211 to common node 230 in response to select inputs S0 and S1, respectively. Only one of the select inputs is asserted at any particular time. The input of output buffer 235, which is shown as an inverter, is coupled to the common node 230. Output buffer 235 outputs an output signal via data output 207 in response to the voltage at common node 230.
The voltage at common node 230 is determined by the output voltage of the selected input buffer and the RC time constant of common node 230. The output voltage of an input buffer swings between logic voltage levels (e.g. 0.0 volts and 3.3 volts) in response to the input signal at the input of the input buffer. The RC time constant of common node 230 is determined by the number of pass gates connected to common node 230, the load presented by each pass gate, and the parasitic capacitance of the conductor that comprises common node 230. As the number inputs N grows, the number of pass gates and the size of common node 230 increases, which increases the loading and the RC time constant of common node 230. As the RC time constant increases, the amount of time required for common node 230 to transition between logic states also increases, which slows the overall operation of multiplexer 200.
According to the multiplexer architecture of multiplexer 200, each pass gate is a complementary switch that comprises a p-channel transistor 240 having its source and drain coupled to the source and drain of an n-channel transistor 245. The select signal of each pass gate is connected directly to the gate of the n-channel transistor 245 and coupled via an inverter 250 to the gate of p-channel transistor 240. The advantage of complementary switch pass gates is that the voltage at common node 230 can swing between the full logic values output by the connected input buffer. One disadvantage of complementary switch pass gates is increased loading of common node 230.
FIG. 3 shows an alternative static multiplexer architecture of the prior art wherein each pass gate comprises a single n-channel transistor. Multiplexer 300 is shown as generally comprising N input buffers 310-311, N pass gates 320-321 controlled by N select inputs S0 and S1, and a single output buffer 335, wherein N is again equal to two. Using a single transistor as a pass gate results in reduced loading of common node 330 when compared to the complementary pass gate architecture of FIG. 2. Furthermore, single transistor pass gates requires less semiconductor die area to implement when compared to complementary transistor pass gates. Unfortunately, using n-channel transistors as pass gates limits the maximum voltage of common node 330 to a voltage of (VCC-V.sub.tn), wherein VCC is the operating voltage V.sub.tn is the threshold voltage of the n-channel transistor that comprises a pass gate. As the value of the operating voltage VCC for integrated circuits continues to decrease, a voltage drop of V.sub.tn becomes increasingly significant.
For occasions wherein the number of signals N must be large and high speed operation is desired, Using a single prior art N-to-1 multiplexer is impractical because of the large RC time constant of the common node and the correspondingly slowed operation of the multiplexer. FIG. 4 shows an arrangement wherein two or more smaller multiplexers may be linked to functionally operate as a single N-to-1 multiplexer. Breaking a single N-to-1 multiplexer into several smaller multiplexers reduces the loading at each of the common nodes of the smaller multiplexers, which increases the speed of operation for each smaller multiplexer when compared to the single N-to-1 multiplexer.
FIG. 4 shows a multiplexing arrangement comprising two m-to-1 multiplexers 406 and 407, wherein m is equal to N/2, each having its output coupled to an input of a two-to-1 multiplexer 408. Multiplexer 408 is provided because the voltage at the common node of a multiplexer is ultimately determined by the data signal that is selected to be passed by the multiplexer. For multiplexing arrangement 400, only one of the multiplexers 406 and 407 is selected at any one time, and the common node of the unselected multiplexer is left to float at whatever voltage it was previously charged to. Therefore, a logic gate such as an OR gate or a NOR gate may not be used to combine the outputs of multiplexers 406 and 407 because the output of the unselected multiplexer cannot be predicted.
There are several disadvantages associated with multiplexing arrangement 400. First, decoding logic 415 is more complex than the decoding logic of a single N-to-1 multiplexer and requires more semiconductor die area to implement. Furthermore, having multiple multiplexers greatly complicates the layout of multiplexing arrangement 400. For example, it is desirable to maintain the shortest signal path possible between data inputs 405 and data output 410, but the select inputs of the multiplexers must be routed to the pass gates. It is difficult to provide a compact layout having the shortest possible signal path, and implementing multiplexing arrangement 400 therefore presents an imposing task when semiconductor die area is limited.